Low-Level Advanced Design of True Random Number Generators Based on Truly Chaotic Digital Nonlinear Oscillators in FPGAs

Tommaso Addabbo, Ada Fort, Riccardo Moretti, Marco Mugnaini, Valerio Vignoli
Department of Information Engineering and Mathematics, University of Siena, Italy

Supplementary Material

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity CHAOTIC_DNO is
  port (
    CLK : in std_logic;
    RST : in std_logic;
    RND_OUT : out std_logic );
end CHAOTIC_DNO;

architecture Behavioral of CHAOTIC_DNO is
  component ELB1NOT is
    port (
      A : in std_logic;
      NOT_A : out std_logic );
  end component;
  component ELB2NOT is
    port (
      A : in std_logic;
      NOT_A : out std_logic );
  end component;
  component ELB3NOT is
    port (
      A : in std_logic;
      NOT_A : out std_logic );
  end component;
  component ELB4XOR3 is
    port (
      A : in std_logic;
      B : in std_logic;
      C : in std_logic;
      XOR_ABC : out std_logic );
  end component;
  component ELB5XOR2 is
    port (
      A : in std_logic;
      B : in std_logic;
      XOR_AB : out std_logic );
  end component;
  component ELB6NXOR2 is
    port (
      A : in std_logic;
      B : in std_logic;
      NXOR_AB : out std_logic );
  end component;
  component ELB7BUFF is
    port (
      A : in std_logic;
      BUFF_A : out std_logic );
  end component;
  component SYNC_INT is
    port (
      ANALOG_IN : in std_logic;
      CLK : in std_logic;
      RST : in std_logic;
      RND_OUT : out std_logic );
  end component;
  signal wire : std_logic_vector(6 downto 0);
begin
  NOT_1 : ELB1NOT
    port map (
      A => wire(0),
      NOT_A => wire(1) );
  NOT_2 : ELB2NOT
    port map (
      A => wire(1),
      NOT_A => wire(2) );
  NOT_3 : ELB3NOT
    port map (
      A => wire(2),
      NOT_A => wire(0) );
  XOR3 : ELB4XOR3
    port map (
      A => wire(0),
      B => wire(3),
      C => wire(4),
      XOR_ABC => wire(5) );
  XOR2 : ELB5XOR2
    port map (
      A => wire(3),
      B => wire(5),
      XOR_AB => wire(3) );
  NXOR : ELB6NXOR2
    port map (
      A => wire(4),
      B => wire(5),
      NXOR_AB => wire(4) );
  BUFF : ELB7BUFF
    port map (
      A => wire(5),
      BUFF_A => wire(6) );
  SYNC : SYNC_INT
    port map (
      ANALOG_IN => wire(6),
      CLK => CLK,
      RST => RST,
      RND_OUT => RND_OUT );
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity SYNC_INT is
  port (
    ANALOG_IN : in std_logic;
    CLK : in std_logic;
    RST : in std_logic;
    RND_OUT : out std_logic );
end SYNC_INT;

architecture Behavioral of SYNC_INT is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of BitRegister : label is "yes";
  attribute KEEP_HIERARCHY of BitRegister : label is "yes";
  attribute BEL of BitRegister : label is "DFF";
  attribute LOC of BitRegister : label is "SLICE_X1Y0";
begin
  BitRegister : FDRE
    generic map (
      INIT => '0' )
    port map (
      Q => RND_OUT,
      C => CLK,
      CE => '1',
      R => RST,
      D => ANALOG_IN );
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB1NOT is
  port (
    A : in std_logic;
    NOT_A : out std_logic );
end ELB1NOT;

architecture Behavioral of ELB1NOT is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of NOTGate : label is "yes";
  attribute KEEP_HIERARCHY of NOTGate : label is "yes";
  attribute BEL of NOTGate : label is "A6LUT";
  attribute LOC of NOTGate : label is "SLICE_X0Y0";
begin
  NOTGate : LUT1
    generic map (
      INIT => "01" )
    port map (
      O => NOT_A,
      I0 => A );
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB2NOT is
  port (
    A : in std_logic;
    NOT_A : out std_logic );
end ELB2NOT;

architecture Behavioral of ELB2NOT is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of NOTGate : label is "yes";
  attribute KEEP_HIERARCHY of NOTGate : label is "yes";
  attribute BEL of NOTGate : label is "B6LUT";
  attribute LOC of NOTGate : label is "SLICE_X0Y0";
begin
  NOTGate : LUT1
    generic map (
      INIT => "01" )
    port map (
      O => NOT_A,
      I0 => A );
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB3NOT is
  port (
    A : in std_logic;
    NOT_A : out std_logic );
end ELB3NOT;

architecture Behavioral of ELB3NOT is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of NOTGate : label is "yes";
  attribute KEEP_HIERARCHY of NOTGate : label is "yes";
  attribute BEL of NOTGate : label is "C6LUT";
  attribute LOC of NOTGate : label is "SLICE_X0Y0";
begin
  NOTGate : LUT1
    generic map (
      INIT => "01" )
    port map (
      O => NOT_A,
      I0 => A );
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB4XOR3 is
  port (
    A : in std_logic;
    B : in std_logic;
    C : in std_logic;
    XOR_ABC : out std_logic );
end ELB4XOR3;

architecture Behavioral of ELB4XOR3 is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of XOR3Gate : label is "yes";
  attribute KEEP_HIERARCHY of XOR3Gate : label is "yes";
  attribute BEL of XOR3Gate : label is "D6LUT";
  attribute LOC of XOR3Gate : label is "SLICE_X0Y0";
begin
  XOR3Gate : LUT3
    generic map (
      INIT => "10010110" )
    port map (
      O => XOR_ABC,
      I0 => A,
      I1 => B,
      I2 => C );
end Behavioral;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB5XOR2 is
  port (
    A : in std_logic;
    B : in std_logic;
    XOR_AB : out std_logic );
end ELB5XOR2;

architecture Behavioral of ELB5XOR2 is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of XORGate : label is "yes";
  attribute KEEP_HIERARCHY of XORGate : label is "yes";
  attribute BEL of XORGate : label is "A6LUT";
  attribute LOC of XORGate : label is "SLICE_X1Y0";
begin
  XORGate : LUT2
    generic map (
      INIT => "0110" )
    port map (
      O => XOR_AB,
      I0 => A,
      I1 => B );
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB6NXOR2 is
  port (
    A : in std_logic;
    B : in std_logic;
    NXOR_AB : out std_logic );
end ELB6NXOR2;

architecture Behavioral of ELB6NXOR2 is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of NXORGate : label is "yes";
  attribute KEEP_HIERARCHY of NXORGate : label is "yes";
  attribute BEL of NXORGate : label is "B6LUT";
  attribute LOC of NXORGate : label is "SLICE_X1Y0";
begin
  NXORGate : LUT2
    generic map (
      INIT => "1001" )
    port map (
      O => NXOR_AB,
      I0 => A,
      I1 => B );
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ELB7BUFF is
  port (
    A : in std_logic;
    BUFF_A : out std_logic );
end ELB7BUFF;

architecture Behavioral of ELB7BUFF is
  attribute DONT_TOUCH : string;
  attribute KEEP_HIERARCHY : string;
  attribute BEL : string;
  attribute LOC : string;
  attribute DONT_TOUCH of Behavioral: architecture is "yes";
  attribute KEEP_HIERARCHY of Behavioral: architecture is "yes";
  attribute DONT_TOUCH of BitBuffer : label is "yes";
  attribute KEEP_HIERARCHY of BitBuffer : label is "yes";
  attribute BEL of BitBuffer : label is "D6LUT";
  attribute LOC of BitBuffer : label is "SLICE_X1Y0";
begin
  BitBuffer : LUT1
    generic map (
      INIT => "10" )
    port map (
      O => BUFF_A,
      I0 => A );
end Behavioral;